VSC7216-01 查看數據表（PDF） - Vitesse Semiconductor

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VSC7216-01

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7216-01

Multi-Gigabit Interconnect Chip

The data coming from the decoder is clocked into the elastic buffer by the recovered clock from the

channel’s CRU. The data is clocked out of the elastic buffers with word clock. If the transmitting device’s

REFCLK is not precisely frequency-locked to a receive channel’s word clock, the channel’s elastic buffer will

tend to gradually fill or empty as the recovered clock (which is by definition frequency-locked to the

transmitter’s REFCLK) steadily drifts in phase relative to the word clock.

In order to accommodate frequency differences between a transmitter’s REFCLK and the word clock, the

VSC7216-01 can automatically perform rate matching by either deleting or duplicating IDLE characters. The

FLOCK input must be LOW to enable rate matching which, based on how the WSI input is connected, can

either be performed in each channel individually or can be performed in parallel across a group of channels that

are word-aligned. This is discussed in detail in the Word Alignment section below. It is the user’s responsibility

to ensure that the frequency at which IDLEs are simultaneously transmitted on each channel accommodates the

frequency differences, if any, in their system architecture. Not meeting the IDLE density requirements could

result in Underrun/Overrun Errors. However, the use of a continuous stream of IDLE characters should be

avoided when rate matching is enable. The IDLE addition/deletion logic relies on the status bits (see Table 8 for

details) to identify K28.5 IDLE characters. The use of continuous IDLE characters will force the VSC7216-01

into the RESYNC state (see Figure 9) resulting in a status bit sequence which the addition/deletion logic does

not recognize as an IDLE character.

The elastic buffer is designed to allow a maximum phase drift of +2 or -2 serial clock bit times between re-

synchronizations, which sets a limit on the maximum data “packet” length allowed between IDLEs. This

maximum packet length depends on the frequency difference between the transmitting and receiving device’s

REFCLKs. Let ∆φ represent phase drift in bit times, and let 2π represent one full 10-bit character of phase

drift. Limiting phase drift to two bit times means the following inequality must be satisfied:

(1)

∆φ ≤ (0.2 × 2π)

Let L be the number of 10-bit characters transmitted, and let ∆f be the frequency offset in ppm. The total

phase drift in bit times is given by:

(2)

∆φ = (∆f ⁄ 106) × 2πL

A simple expression for maximum packet length as a function of frequency offset is derived by substituting

(2) in (1) and solving for L:

(3)

L ≤ (0.2 × 106) ⁄ ∆f

As an example, if the frequency offset is 200ppm, the maximum packet length should not be more than 1K

bytes. To increase the maximum packet length L, decrease the frequency offset ∆f. Please note that if only one

K28.5 is transmitted between “packets” of data, it might be dropped during compensation for phase drift. If the

user must have at least one K28.5 between these two packets, then two K28.5s must be transmitted.

Word Alignment

The VSC7216-01 performs channel-to-channel word alignment. In this mode of operation, if the data from

all four channels on the transmitting VSC7216-01 (e.g., the 4 Tn(7:0) busses) is viewed as a 32-bit word, then

the receiving VSC7216-01 will recover an identical word. For example, if a transmit pattern was ‘ABCD’,

G52352-0, Rev 3.2

05/05/01

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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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