VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor
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VSC9110SA Datasheet PDF : 24 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
STS-48 Physical Layer
ATM UNI/NNI Device
Figure 4: Tx UTOPIA Interface Timing Dependencies
TUCLK
TUDATA[31..0]
TUPRTY
TUSOC
TUENB*
TUFULL*/TUCLAV
TUCLKO
TSU,TUIN
TH,TUIN
TP,TUOUT
TP,TUCLKO
Data Sheet
VSC9110
Table 4: Tx UTOPIA Interface
Symbol
Description
Min
fTUCLK
dcTUCLK
TR/F, TUCLK
TSU, TUIN
TUCLK clock frequency (nominal)
50
TUCLK duty cycle
40
TUCLK rise/fall time
-
TUDATA[31..0], TUPRTY, TUSOC and TUENB* setup time to
TUCLK rising edge
2.0
TH, TUIN
TUDATA[15..0], TUPRTY, TUSOC and TUENB* hold time to
TUCLK rising edge
0.5
TD, TUOUT
TUCLK rising edge to TUFULL*/TUCLAV valid
1.0
TP, TUCLKO
TUCLKO rising edge to TUFULL*/TUCLAV valid.
0.0
Outputs are for 25 pF load.
Max
104
60
2.0
-
-
6.0
1.5
Unit
MHz
%
ns
ns
ns
ns
ns
Page 10
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52198-0, Rev. 4.2
1/8/00
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