VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor

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VSC9110SA

STS-48 Physical Layer ATM UNI/NNI Device

Vitesse Semiconductor 

Data Sheet

VSC9110

Features

VITESSE

SEMICONDUCTOR CORPORATION

STS-48 Physical Layer

ATM UNI/NNI Device

• STS-48c ATM Framing Device for User Net-

work Interface and Network Node Interface

Applications

• STS-48c / STM-16c Support. Terminates and

Generates SONET/SDH Section, Line, and

Path Layers

• UTOPIA-3 Interface

• 16 bit PECL Interface to High-speed MUX/

DEMUX Transceivers

• Generic 8-bit Microprocessor Interface

• +3.3V Power Supply

• +5V Tolerant TTL I/O

• Compliant with SONET and SDH Require-

ments as Stated in ANSI T1.105, Bellcore

GR-253-CORE and ITU-T G.707 Documents

• 0.35 Micron CMOS Technology

• Thermally Enhanced 256 BGA Package

• Provides JTAG TAP Controller Conforming to

the IEEE 1149.1 Standard

VSC9110 Block Diagram

TLCLK+/-

TLOUT[15..0]+/-

TLPRTY+/-

TLCLKOUT+/-

RLCLK+/-

RLIN[15..0]+/-

RLPRTY+/-

JTAG TAP

SONET/SDH

Section (RSOH)

Generation

TSOP

SONET/SDH

Line (MSOH)

Generation

TLOP

STS-48C

SPE/VC-4-16c

Path Gener.

TPOP

ATM cell

Mappng

TACP

Tx FIFO

SONET/SDH

Section Trace

Buffer

SSTB

SONET/SDH

Path Trace

Buffer

SPTB

SONET/SDH

SONET/SDH

STS-48C

ATM cell

Section (RSOH)

Line (MSOH)

SPE/VC-4-16c

Demappng

Termination

Termination

Path Term.

LIF

RSOP

RLOP

RPOP

RACP

Rx FIFO

TUDATA[31..0]

TUPRTY

TUSOC

TUENB*

TUFULL*/TUCLAV

TUCLK

TUCLKO

RUDATA[31..0]

RUPRTY

RUSOC

RUENB*

RUEMPTY*/RXCLAV

RUCLK

UIF

RUCLKO

BERM

CPU

GPIOO[3..0]

GPIOI[1..0]

G52198-0, Rev. 4.2

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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