VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC9110SA

STS-48 Physical Layer ATM UNI/NNI Device

Vitesse Semiconductor 

Data Sheet

VSC9110

VITESSE

SEMICONDUCTOR CORPORATION

STS-48 Physical Layer

ATM UNI/NNI Device

• The Automatic Protection Switching (APS) bytes, K1 and K2, are extracted and filtered. Unstable alarm

is supported. The filter constants are programmable.

Receive Path Overhead Processor (RPOP)

• The H1 and H2 pointer bytes are detected and interpreted according to ANSI T1.105 and ITU-T G.707.

The mechanism is programmable to support both SONET and SDH. Path Alarm Indication Signal (AIS-

P) and Loss of Pointer (LOP-P) alarm declarations are provided. Several pointer functions are also pro-

vided for diagnostic purposes.

• The H1 and H2 pointer bytes are monitored for Concatenation Indication (CI). Loss of Pointer (LOPX)

and AIS (AISX) alarm declarations are provided.

• Path BIP-8 errors carried in the B3 byte are detected and accumulated. Both individual and block mode

accumulation of B3 errors are supported.

• Path REI error indications carried in the G1 byte are detected and accumulated. Up to 64000 individual

errors can be detected per second. Both individual and block mode accumulation of Path REI error indi-

cations are supported.

• The Path RDI carried in the G1 byte is detected and programmable.

• The Signal Label carried in the C2 byte is detected, alarmed and is programmable.

Receive ATM Cell Processor (RACP)

• Cell Delineation is provided using shortened cyclic code with a generating polynomial 1 + x + x2 + x8.

The coset polynomial 1 + x2 + x4 + x8 can be added to the calculated HEC check bits before comparison.

• Single-bit header error correction is supported. The dropping of cells during single or multiple error

detection is programmable.

• The 48 byte information field is descrambled with a self-synchronizing descrambler polynomial 1 + x43.

Descrambling can be enabled/disabled.

• Cells can be filtered based on a programmable cell header pattern in the GFC, PTI, or CLP fields.

• The number of correctable and uncorrectable HEC errors detected, and the number of cells written to the

Rx FIFO are monitored.

• The Rx FIFO can accommodate storage of eight ATM cells.

Drop Side Interface (ATM UTOPIA Interface)

• A parity bit, programmable for even/odd parity, is provided for each transmit and receive datapaths.

• It is possible to force reset/flush the contents in the Tx FIFO via the CPU interface.

• It is possible to force reset/flush the contents in the Rx FIFO via the CPU interface.

• The Drop Side Interface provides a Single-PHY UTOPIA-3 interface for ATM operations.

• Two formats of the ATM cells are supported: 52 byte cell or 56 byte cell containing the HEC.

• The UTOPIA-3 interface supports both word-level and cell-level flow control.

G52198-0, Rev. 4.2

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 3

Share Link: