VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor

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VSC9110SA

STS-48 Physical Layer ATM UNI/NNI Device

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

STS-48 Physical Layer

ATM UNI/NNI Device

Data Sheet

VSC9110

Transmit ATM Cell Processor (TACP)

• The ATM cells are mapped into the STS-48c SPE or equivalent SDH VC-16-16c. Programmable idle/

unassigned cells are inserted into the cell stream.

• The 48 byte information field is scrambled with a self-synchronizing descrambler polynomial 1 + x43.

Scrambling can be enabled/disabled.

• The HEC generator performs a CRC-8 calculation over the first four header octets using the generating

polynomial 1 + x + x2 + x8. The coset polynomial 1 + x2 + x4 +x6 can be added to the result. The HEC

is optionally inserted into the fifth octet of the header of cells read from the Tx FIFO.

• The Tx FIFO can accomodate storage of eight ATM cells.

Transmit Path Overhead Processor (TPOP)

• The H1 and H2 pointer byte values are programmable to support both SONET and SDH. Several pointer

functions are provided for diagnostics purposes. The remaining 47 H1 and H2 bytes are programmable.

• The Path BIP-8 is computed and placed in the B3 byte of the current frame. It is possible to insert B3

errors for diagnostic purposes.

• The number of Path BIP-8 errors detected in the Receive Path Overhead Processor (RPOP) is backre-

ported as Path REI in the G1 byte. Both individual and block mode backreporting for G1 are supported.

• It is possible to enable/disable RDI-P insertion for each of the following alarms: LOS, LOF, AIS-L, AIS-

P, LOP-P, TIM-P, UNEQ-P, LCD-P and PLM-P. Both the latest and earlier definitions of RDI-P are sup-

ported.

• The Path Signal Label (C2) byte value is programmable.

• The Path Trace (J1) byte value is programmable.

• The F2, H4, Z3, Z4, and Z5 bytes are programmable.

Transmit Line Overhead Processor (TLOP)

• It is possible to insert programmable sets of K1 and K2 bytes into the outgoing data stream.

• RDI-L can be automatically inserted during the detection of an LOS, LOF, or AIS-L alarm in the receive

data stream.

• The Line BIP-384 code is computed and placed in the B2 bytes of the current frame. It is possible to

insert B2 errors for diagnostics purposes.

• The number of Line BIP-384 errors detected in the Receive Line Overhead Processor (RLOP) is backre-

ported as Line REI in the M1 byte. Up to 255 errors can be backreported per frame in individual mode.

Both individual and block mode backreporting for M1 are supported. It is possible to insert M1 error

indications for diagnostics purposes.

• The Synchronization Status value inserted in the S1 byte is programmable.

• All bytes in the line overhead that are reserved for national or future international standardization use can

be overwritten with 0x00.

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52198-0, Rev. 4.2

1/8/00

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