VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor

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VSC9110SA

STS-48 Physical Layer ATM UNI/NNI Device

Vitesse Semiconductor 

Data Sheet

VSC9110

VITESSE

SEMICONDUCTOR CORPORATION

STS-48 Physical Layer

ATM UNI/NNI Device

• The H1, H2, and H3 bytes from the Transmit Overhead Access Port (TOAP) can be inserted into the H1,

H2, and H3 overhead bytes, or applied as an error mask to the H1, H2, and H3 overhead bytes.

Transmit Section Overhead Processor (TSOP)

• It is possible to forced insert all "1"s into the data stream, before scrambling, with the exception of the sec-

tion overhead. The AIS-L condition can be automatically inserted through activity from the special pur-

pose serial interfaces.

• The Section BIP-8 code is computed and can be placed in the B1 byte of the current frame. It is possible

to insert B1 errors for diagnostics purposes.

• The A1 and A2 framing bytes can be inserted into the frame. It is also possible to introduce bit errors in

the framing word.

• The J0 byte supports both SONET and SDH formats. The J0 byte can be programmed to a fixed value for

interworking with older equipment implementing the C1 indentification byte.

• The Z0 growth bytes supports both SONET and SDH formats. The Z0 bytes can be programmed to carry

the C1 identification bytes for interworking with older equipment.

• The outgoing data stream is optionally scrambled using the generating polynomial 1 + x6 + x7 with a

sequence length of 127.

• It is possible to force insert all “0”s in the outgoing data stream after scrambling for diagnostic purposes

(LOS).

• All bytes in the section overhead that are reserved for national or future international standardization use

can be overwritten with 0x00.

SONET/SDH Section Trace Buffers (SSTB)

• Three different Section Trace Message (J0) formats are supported in both transmit and receive directions:

one byte (SONET) message, 16 byte (SDH) message, and 64 byte (SONET CLLI) message.

• The received section trace message is checked for persistency. A mismatch alarm is supported.

CPU Interface

• All configuration bits are both writeable and readable and can be accessed regardless of the device clock

source status, except for the reset state. Configuration bits include selection bits, interrupt masking bits,

and programmable counter/control values.

• Eight programmable General Purpose Input/Output (GPIO) ports are available for monitoring and con-

trolling external signals. All GPIOs support bistable interrupts when configured as input ports.

• Clock activity monitors are implemented for all input clocks.

Bit Error Rate Monitoring

• Bit error rate monitoring is based on the Line BIP (B2) error code and is capable of measuring BERs

down to 10-10 .

• Two bit error rate thresholds are implemented on the device.

G52198-0, Rev. 4.2

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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