VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor

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VSC9110SA

STS-48 Physical Layer ATM UNI/NNI Device

Vitesse Semiconductor 

STS-48 Physical Layer

ATM UNI/NNI Device

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC9110

JTAG

• Standard IEEE 1149.1 compliant JTAG interface.

Loopback Modes

• Equipment loopback is supported by looping the output from the Transmit Section Overhead Processor

(TSOP), in the transmit direction, back to the input of the Receive Section Overhead Processor (RSOP),

in the receive direction.

• Facility loopback is supported by looping the data received on the receive Line Side Interface back to the

transmit Line Side Interface.

• Utopia loopback is supported by looping the output from the Tx FIFO to the input of the Rx FIFO.

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52198-0, Rev. 4.2

1/8/00

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