VSC9110SA 查看數據表（PDF） - Vitesse Semiconductor
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VSC9110SA Datasheet PDF : 24 Pages
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Data Sheet
VSC9110
VITESSE
SEMICONDUCTOR CORPORATION
STS-48 Physical Layer
ATM UNI/NNI Device
Figure 3: Rx UTOPIA Interface Timing Dependencies
RUCLK
RUENB*
TSU,RUIN
TH,RUIN
RUDATA[31..0]
RUPRTY
RSOC
RUEMPTY*/
RUCLAV
RUCLKO
TP,RUOUT
TP,RUCLKO
Table 3: Rx UTOPIA Interface
Symbol
Description
fRUCLK
dc RUCLK
TR/F, RUCLK
TSU, RUIN
TH, RUIN
TP, RUOUT
RUCLK clock frequency (nominal)
RUCLK duty cycle
RUCLK rise/fall time
RUENB* setup time to RUCLK rising edge
RUENB* hold time to RUCLK rising edge
RUCLK rising edge to RUDATA[31..0], RUPRTY, RUSOC,
RUEMPTY*/RUCLAV valid
TP, RUCLKO
RUCLKO rising edge to RUDATA[31..0], RUPRTY, RUSOC
and RUEMPTY*/RUCLAV valid.
Output times are for 25 pF load.
Min Max Unit
50
104
MHz
40
60
%
-
2.0
ns
2.0
-
ns
0.5
-
ns
1.0
6.0
ns
0.0
1.5
ns
G52198-0, Rev. 4.2
1/8/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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