CYS25G0101DX-AEXC 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CYS25G0101DX-AEXC

SONET OC-48 Transceiver

Cypress Semiconductor 

CYS25G0101DX

Logic Block Diagram

(155.52 MHz)

TXCLKI TXD[15:0]

FIFO_RST

16

FIFO_ERR

TXCLKO

(155.52 MHz)

REFCLK

(155.52 MHz)

RXCLK

RXD[15:0]

16

LOOPTIME

Input

Register

TX PLL

X16

FIFO

16

Shifter

TX Bit-Clock

Output

Register

16

Shifter

Recovered

Bit-Clock

Lock-to-Ref

RX CDR

PLL

Retimed

Data

DIAGLOOP

LINELOOP

LOOPA

Lock-to-Data/

Clock Control

Logic

OUT

PWRDN LOCKREF SD LFI RESET IN

Document Number: 38-02009 Rev. *O

Page 2 of 22

Share Link: