F81865F 查看數據表（PDF） - Feature Integration Technology Inc.
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F81865F Datasheet PDF : 128 Pages
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Transmitter Holding Register ⎯ Base + 0
Bit
Name
R/W Default
7-0
THR
Data to be transmitted.
W 00h Write only when LCR[7] is 0
Description
F81865
Divisor Latch (LSB) ⎯ Base + 0
Bit
Name
R/W Default
Description
Baud generator divisor low byte.
7-0
DLL
R/W 01h Access only when LCR[7] is 1.
Divisor Latch (MSB) ⎯ Base + 1
Bit
Name
R/W Default
Description
Baud generator divisor high byte.
7-0
DLM
R/W 00h
Access only when LCR[7] is 1.
Interrupt Enable Register (IER) ⎯ Base + 1
Bit
Name
R/W Default
Description
7-5
Reserved
-
- Reserved.
This bit is used only in 9-bit mode and always returns “0” when 9-bit mode is
disabled.
4
SM2
R/WC 0 0: The receiver could receive data byte.
1: The receiver could only receive address byte and issue an interrupt when
the address is received.
3
EDSSI
R/W 0 Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2
ELSI
R/W 0 Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1
ETBFI
R/W
0
Enable Transmitter Holding Register Empty Interrupt. Access only when
LCR[7] is 0.
0
ERBFI
R/W 0 Enable Received Data Available Interrupt. Access only when LCR[7] is 0.
Interrupt Identification Register (IIR) ⎯ Base + 2
Bit
Name
R/W Default
Description
0: FIFO is disabled
7
FIFO_EN
R
0
1: FIFO is enabled.
0: FIFO is disabled
6
FIFO_EN
R
0 1: FIFO is enabled.
5-4
Reserved
-
- Reserved.
3-1
IRQ_ID
000: Interrupt is caused by Modem Status
001: Interrupt is caused by Transmitter Holding Register Empty
R
00 010: Interrupt is caused by Received Data Available.
110: Interrupt is caused by Character Timeout
011: Interrupt is caused by Line Status.
1: Interrupt is not pending.
0
IRQ_PENDN
R
1
0: Interrupt is pending.
35
May, 2010
V0.28P
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