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F81865F 查看數據表(PDF) - Feature Integration Technology Inc.

零件编号
产品描述 (功能)
生产厂家
F81865F
FINTEK
Feature Integration Technology Inc. FINTEK
F81865F Datasheet PDF : 128 Pages
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Parallel Port Data Register Base + 0
Bit
Name
R/W Default
Description
7-0
DATA
R/W 00h The output data to drive the parallel port data lines.
F81865
ECP Address FIFO Register Base + 0
Bit
Name
R/W Default
Description
Access only in ECP Parallel Port Mode and the ECP_MODE programmed in
the Extended Control Register is 011.
The data written to this register is placed in the FIFO and tagged as an
Address/RLE. It is auto transmitted by the hardware. The operation is only
defined for forward direction. It divide into two parts :
7-0
ECP_AFIFO
R/W 00h Bit 7 :
0: bits 6-0 are run length, indicating how many times the next byte to appear (0
= 1time, 1 = 2times, 2 = 3times and so on).
1: bits 6-0 are ECP address.
Bit 6-0 : Address or RLE depends on bit 7.
Device Status Register Base + 1
Bit
Name
R/W Default
Description
7
BUSY_N
R
- Inverted version of parallel port signal BUSY.
6
ACK_N
R
- Version of parallel port signal ACK#.
5
PERROR
R
- Version of parallel port signal PE.
4
SELECT
R
- Version of parallel port signal SLCT.
3
ERR_N
R
- Version of parallel port signal ERR#.
2-1
Reserved
R
11 Reserved. Return 11b when read.
This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0
TMOUT
R
-
0: no time out error.
1: time out error occurred, write 1 to clear.
Device Control Register Base + 2
Bit
Name
R/W Default
Description
7-6
Reserved
-
11 Reserved. Return 11b when read.
0: the parallel port is in output mode.
5
DIR
R/W 0 1: the parallel port is in input mode.
It is auto reset to 1 when in SPP mode.
4
ACKIRQ_EN
R/W 0 Enable an interrupt at the rising edge of ACK#.
Inverted and then drives the parallel port signal SLIN#.
3
SLIN
R/W 0
When read, the status of inverted SLIN# is return.
Drives the parallel port signal INIT#.
2
INIT_N
R/W 0
When read, the status of INIT# is return.
Inverted and then drives the parallel port signal AFD#.
1
AFD
R/W 0
When read, the status of inverted AFD# is return.
38
May, 2010
V0.28P

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