F81865F 查看數據表（PDF） - Feature Integration Technology Inc.
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F81865F Datasheet PDF : 128 Pages
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6-4
IMPID
3
Reserved
2
BYTETRAN_N
1-0
Reserved
F81865
000: the design is 16-bit implementation.
001: the design is 8-bit implementation (default).
R 001 010: the design is 32-bit implementation.
011-111: Reserved.
Only valid in ECP and ECP_MODE is 111b.
-
- Reserved.
0: when transmitting there is 1 byte waiting in the transceiver that does not
affect the FIFO full condition.
R
1 1: when transmitting the state of the full bit includes the byte being transmitted.
Only valid in ECP and ECP_MODE is 111b.
Return 00 when read.
R 00
Only valid in ECP and ECP_MODE is 111b.
ECP Configuration Register B ⎯ Base + 401h
Bit
Name
R/W Default
Description
0: only send uncompressed data.
7
COMP
R
0 1: compress data before sending.
Only valid in ECP and ECP_MODE is 111b.
Reserved. Return 1 when read.
6
Reserved
R
1
Only valid in ECP and ECP_MODE is 111b.
5-3
ECP_IRQ_CH
000: the interrupt selected with jumper.
001: select IRQ 7 (default).
010: select IRQ 9.
011: select IRQ 10.
R 001 100: select IRQ 11
101: select IRQ 14.
110: select IRQ 15.
111: select IRQ 5.
Only valid in ECP and ECP_MODE is 111b.
2-0 ECP_DMA_CH
Return the DMA channel of ECP parallel port.
R 011
Only valid in ECP and ECP_MODE is 111b.
Extended Control Register ⎯ Base + 402h
Bit
Name
R/W Default
Description
000: SPP Mode.
001: PS/2 Parallel Port Mode.
010: Parallel Port Data FIFO Mode.
011: ECP Parallel Port Mode.
7-5
ECP_MODE
R/W 000 100: EPP Mode.
101: Reserved.
110: Test Mode.
111: Configuration Mode.
Only valid in ECP.
0: disable the interrupt generated on the falling edge of ERR#.
4
ERRINTR_EN R/W 0
1: enable the interrupt generated on the falling edge of ERR#.
0: disable DMA.
3
DAMEN
R/W 0
1: enable DMA. DMA starts when SERVICEINTR is 0.
40
May, 2010
V0.28P
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