LXT970ATC 查看數據表（PDF） - Intel

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LXT970ATC

Dual-Speed Fast Ethernet Transceiver

Intel 

Dual-Speed Fast Ethernet Transceiver — LXT970A

Table 2. LXT970A MII Signal Descriptions

Pin#1

Pin Name

I/O2,3

Signal Description4

MII Data Interface Pins

63

TXD4

62

TXD3

Transmit Data. The Media Access Controller (MAC) drives data to the

61

TXD2

I

LXT970A using these inputs. TXD4 is monitored only in Symbol (5B) Mode.

60

TXD1

These signals must be synchronized to the TX_CLK.

59

TXD0

58

TX_EN

I

Transmit Enable. The MAC asserts this signal when it drives valid data on the

TXD inputs. This signal must be synchronized to the TX_CLK.

Transmit Clock. Normally the LXT970A drives TX_CLK; in Slave Clock Mode,

TX_CLK is an input. Refer to the Clock Requirements discussion in the

57

TX_CLK

I/O Functional Description section on page 18.

25 MHz for 100 Mbps operation.

2.5 MHz for 10 Mbps operation.

Transmit Coding Error. The MAC asserts this input when an error has

56

TX_ER

I

occurred in the transmit data stream. When the LXT970A is operating at 100

Mbps, the LXT970A responds by sending invalid code symbols on the line.

46

RXD4

47

RXD3

Receive Data. The LXT970A drives received data on these outputs,

48

RXD2

O synchronous to RX_CLK.

49

RXD1

RXD4 is driven only in Symbol (5B) Mode.

50

RXD0

51

RX_DV

O

Receive Data Valid. The LXT970A asserts this signal when it drives valid data

on RXD. This output is synchronous to RX_CLK.

55

RX_ER

O

Receive Error. The LXT970A asserts this output when it receives invalid

symbols from the network. This signal is synchronous to RX_CLK.

Receive Clock. This continuous clock provides reference for RXD, RX_DV, and

RX_ER signals. Refer to the Clock Requirements discussion in the Functional

54

RX_CLK

O

Description section.

25 MHz for 100 Mbps operation.

2.5 MHz for 10 Mbps operation.

Collision Detected. The LXT970A asserts this output when detecting a

64

COL

O collision. This output remains High for the duration of the collision.

This signal is asynchronous and inactive during full-duplex operation.

Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT970A asserts

1

CRS

O

this output when either transmit or receive medium is non-idle. During full-

duplex operation (bit 0.8 = 1) or repeater operation

(bit 19.13 = 1), CRS is asserted only when the receive medium is non-idle.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.

3. If bit 17.3 = 0, 55Ω series termination resistors are recommended on all output signals to avoid undershoot/overshoot, even

on short traces.

If bit 17.3 = 1, termination resistors are not required.

4. The LXT970A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).

Datasheet

11

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