M24512-WMW6T 查看數據表（PDF） - STMicroelectronics

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M24512-WMW6T

512 Kbit Serial I²C Bus EEPROM

STMicroelectronics 

Figure 9. Read Mode Sequences

CURRENT

ADDRESS

READ

ACK

NO ACK

DEV SEL

DATA OUT

R/W

M24512

RANDOM

ADDRESS

READ

ACK

ACK

ACK

ACK

NO ACK

DEV SEL *

BYTE ADDR BYTE ADDR

DEV SEL *

DATA OUT

R/W

R/W

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

ACK

ACK

DEV SEL

DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

ACK

ACK

ACK

ACK

ACK

DEV SEL *

BYTE ADDR BYTE ADDR

DEV SEL *

DATA OUT 1

R/W

R/W

ACK

NO ACK

DATA OUT N

AI01105C

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

Read Operations

Read operations are performed independently of

the state of the Write Control (WC) signal.

After the successful completion of a Read opera-

tion, the device’s internal address counter is incre-

mented by one, to point to the next byte address.

Random Address Read

A dummy Write is first performed to load the ad-

dress into this address counter (as shown in Fig-

ure 9.) but without sending a Stop condition. Then,

the bus master sends another Start condition, and

repeats the Device Select Code, with the Read/

Write bit (RW) set to 1. The device acknowledges

this, and outputs the contents of the addressed

byte. The bus master must not acknowledge the

byte, and terminates the transfer with a Stop con-

dition.

Current Address Read

For the Current Address Read operation, following

a Start condition, the bus master only sends a De-

vice Select Code with the Read/Write bit (RW) set

to 1. The device acknowledges this, and outputs

the byte addressed by the internal address

counter. The counter is then incremented. The bus

master terminates the transfer with a Stop condi-

tion, as shown in Figure 9., without acknowledging

the byte.

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