NDC7001 查看數據表（PDF） - Fairchild Semiconductor

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NDC7001

Dual N & P-Channel Enhancement Mode Field Effect Transistor

Fairchild Semiconductor 

May 2002

NDC7001C

Dual N & P-Channel Enhancement Mode Field Effect Transistor

General Description

These dual N & P-Channel Enhancement Mode Field

Effect Transistors are produced using Fairchild’s

proprietary, high cell density, DMOS technology. This

very high density process has been designed to

minimize on-state resistance, provide rugged and

reliable performance and fast switching. These

device is particularly suited for low voltage, low

current, switching, and power supply applications.

Features

• Q1 0.51 A, 60V.

• Q2 –0.34 A, 60V.

RDS(ON) = 2 Ω @ VGS = 10 V

RDS(ON) = 4 Ω @ VGS = 4.5 V

RDS(ON) = 5 Ω @ VGS = –10 V

RDS(ON) = 7.5Ω @ VGS = –4.5 V

• High saturation current

• High density cell design for low RDS(ON)

• Proprietary SuperSOTTM –6 package: design using copper

lead frame for superior thermal and electrical capabilities

D2

S1

D1

SuperSOT TM -6

G2

S2

G1

Q2(P)

4

3

5

2

6

1

Q1(N)

Absolute Maximum Ratings TA=25oC unless otherwise noted

Symbol

VDSS

VGSS

ID

Parameter

Drain-Source Voltage

Gate-Source Voltage

Drain Current – Continuous

– Pulsed

(Note 1a)

PD

Power Dissipation for Single Operation

(Note 1a)

(Note 1b)

(Note 1c)

TJ, TSTG

Operating and Storage Junction Temperature Range

Thermal Characteristics

RθJA

Thermal Resistance, Junction-to-Ambient (Note 1a)

RθJC

Thermal Resistance, Junction-to-Case

(Note 1)

Package Marking and Ordering Information

Device Marking

Device

Reel Size

.01C

NDC7001C

7’’

Q1

Q2

60

–60

±20

±20

0.51

–0.34

1.5

–1

0.96

0.9

0.7

–55 to +150

Units

V

A

W

°C

130

°C/W

60

Tape width

8mm

Quantity

3000

2002 Fairchild Semiconductor Corporation

NDC7001C Rev B (W)

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