ARM9TDMI 查看數據表（PDF） - Unspecified

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ARM9TDMI

ARM9TDMI Processor Core

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List of Figures

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ARM9TDMI EmbeddedICE macrocell overview ..................................................... 5-38

Watchpoint control register for data comparison .................................................... 5-39

Watchpoint control register for instruction comparison ........................................... 5-41

Debug control register ............................................................................................ 5-42

Debug status register .............................................................................................. 5-43

Vector catch register ............................................................................................... 5-44

Debug comms control register ................................................................................ 5-47

Single load interlock timing ....................................................................................... 7-5

Two cycle load interlock ............................................................................................ 7-6

LDM interlock ............................................................................................................ 7-7

LDM dependent interlock .......................................................................................... 7-8

ARM9TDMI instruction memory interface output timing ........................................... 8-2

ARM9TDMI instruction address bus enable ............................................................. 8-2

ARM9TDMI instruction memory interface input timing ............................................. 8-3

ARM9TDMI data memory interface output timing ..................................................... 8-4

ARM9TDMI data address bus timing ........................................................................ 8-5

ARM9TDMI data ABORT and DnMREQ timing ........................................................ 8-5

ARM9TDMI data data bus timing .............................................................................. 8-5

ARM9TDMI data bus enable .................................................................................... 8-6

ARM9TDMI miscellaneous signal timing .................................................................. 8-6

ARM9TDMI coprocessor interface signal timing ....................................................... 8-7

ARM9TDMI JTAG output signals .............................................................................. 8-8

ARM9TDMI external boundary scan chain output signals ........................................ 8-9

ARM9TDMI SDOUTBS to TDO relationship ............................................................. 8-9

ARM9TDMI nTRST to RSTCLKBS relationship ..................................................... 8-10

ARM9TDMI JTAG input signal timing ..................................................................... 8-10

ARM9TDMI GCLK related debug output timings .................................................... 8-11

ARM9TDMI TCK related debug output timings ...................................................... 8-12

ARM9TDMI nTRST to DBGRQI relationship .......................................................... 8-12

ARM9TDMI EDBGRQ to DBGRQI relationship ...................................................... 8-12

ARM9TDMI DBGEN to output effects ..................................................................... 8-13

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