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DSP56F807 查看數據表(PDF) - Freescale Semiconductor

零件编号
产品描述 (功能)
生产厂家
DSP56F807
Freescale
Freescale Semiconductor Freescale
DSP56F807 Datasheet PDF : 60 Pages
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2.3 Clock and Phase Locked Loop Signals
Clock and Phase Locked Loop Signals
No. of
Pins
1
1
1
Signal
Name
EXTAL
XTAL
CLKO
Table 2-5 PLL and Clock
Signal
Type
Input
Input/
Output
State During
Reset
Input
Chip-driven
Signal Description
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.4.
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to Section 3.4.
Output
Chip-driven
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.4.2.
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user
can select between outputting a version of the signal applied to XTAL and
a version of the device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 2-6 Address Bus Signals
No. of
Pins
6
2
Signal
Name
A0–A5
A6–A7
Signal
Type
Output
Output
State During
Reset
Tri-stated
Tri-stated
Signal Description
Address Bus—A0–A5 specify the address for external Program or
Data memory accesses.
Address Bus—A6–A7 specify the address for external Program or
Data memory accesses.
GPIOE2- Input/O
GPIOE3 utput
Input
Port E GPIO—These two General Purpose I/O (GPIO) pins can
individually be programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15 Output
Tri-stated Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
GPIOA0- Input/O
GPIOA7 utput
Input
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
11

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