74AHC273PWDH 查看數據表（PDF） - Philips Electronics

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74AHC273PWDH

Octal D-type flip-flop with reset; positive-edge trigger

Philips Electronics 

Philips Semiconductors

Octal D-type flip-flop with reset;

positive-edge trigger

Product specification

74AHC273; 74AHCT273

FEATURES

• Ideal buffer for MOS microcontroller or memory

• Common clock and master reset

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt trigger actions

• Inputs accepts voltages higher than VCC

• See ‘377’ for clock enable version

• See ‘373’ for transparent latch version

• See ‘374’ for 3-state version

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74AHC/AHCT273 are high-speed Si-gate CMOS

devices and are pin compatible with low power Schottky

TTL (LSTTL). They are specified in compliance with

JEDEC standard no. 7A.

The 74AHC/AHCT273 have eight edge-triggered, D-type

flip-flops with individual D inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs load

and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the

LOW-to-HIGH clock transition, is transferred to the

corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock or

data inputs by a LOW on the MR input.

The device is useful for applications where the true output

only is required and the clock and master reset are

common to all storage elements.

QUICK REFERENCE DATA

Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

fmax

CI

CO

CPD

propagation delay

CP to Qn

MR to Qn

maximum clock frequency

input capacitance

output capacitance

power dissipation

capacitance

CL = 15 pF; VCC = 5 V

CL = 15 pF; VCC = 5 V

VI = VCC or GND

CL = 50 pF; f = 1 MHz;

notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑ (CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

TYPICAL

AHC

AHCT

4.2

4.0

3.7

3.9

120

120

3.0

3.0

4.0

4.0

14.0

18.0

UNIT

ns

ns

MHz

pF

pF

pF

1999 Sep 01

2

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