88E1111 查看數據表（PDF） - Marvell Semiconductor
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88E1111 Datasheet PDF : 52 Pages
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88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the
RGMII interface. The MAC interface pins are 3.3V tolerant.
Table 5: RTBI Interface
117-TFBGA 96-BCC
Pin #
Pin #
E2
8
128-PQFP Pin Name
Pin #
14
GTX_CLK/
TXC
H2
16
24
TXD[3]/TD[3]
G3
14
20
TXD[2]/TD[2]
G2
12
19
TXD[1]/TD[1]
F1
11
18
TXD[0]/TD[0]
E1
9
16
TX_EN/
TD4_TD9
C1
2
7
RX_CLK/
RXC
B3
91
125
RXD[3]/RD[3]
C3
93
126
RXD[2]/RD[2]
D3
92
128
RXD[1]/RD[1]
B2
95
3
RXD[0]/RD[0]
B1
94
4
RX_DV/
RD4_RD9
Pin
Ty p e
I
I
I
O, Z
O, Z
O, Z
Description
RGMII Transmit Clock provides a 125 MHz
reference clock with ± 50 ppm tolerance. In
RTBI mode, GTX_CLK is used as TXC.
RTBI Transmit Data.
In RTBI mode, TXD[3:0] are used as
TD[3:0]. TD[3:0] run at double data rate with
bits [3:0] presented on the rising edge of
GTX_CLK, and bits [8:5] presented on the
falling edge of GTX_CLK. In this mode,
TXD[7:4] are ignored.
RTBI Transmit Data.
In RTBI mode, TX_EN is used as TD4_TD9.
TD4_TD9 runs at a double data rate with bit
4 presented on the rising edge of GTX_CLK,
and bit 9 presented on the falling edge of
GTX_CLK.
RTBI Receive Clock provides a 125 MHz ref-
erence clock with ± 50 ppm tolerance
derived from the received data stream. In
RTBI mode, RX_CLK is used as RXC.
RTBI Receive Data.
In RTBI mode, RXD[3:0] are used as
RD[3:0]. RD[3:0] runs at double data rate
with bits [3:0] presented on the rising edge of
RX_CLK, and bits [8:5] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
are ignored.
RTBI Receive Data.
In RTBI mode, RX_DV is used as
RD4_RD9. RD4_RD9 runs at a double data
rate with bit 4 presented on the rising edge
of RX_CLK, and bit 9 presented on the fall-
ing edge of RX_CLK.
Doc. No. MV-S105540-00, Rev. --
Page 18
Document Classification: Proprietary Information
Copyright © 2009 Marvell
March 4, 2009, Advance
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