88E1111 查看數據表（PDF） - Marvell Semiconductor

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88E1111

Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver

Marvell Semiconductor 

Signal Description

Pin Description

Table 6: SGMII Interface

117-TFBGA 96-BCC

Pin #

Pin #

A3

82

A4

81

128-PQFP Pin Name

Pin #

113

S_IN+

112

S_IN-

A5

79

110

S_CLK+

A6

80

109

S_CLK-

A7

77

107

S_OUT+

A8

75

105

S_OUT-

Pin

Type

I

I/O

O, Z

Description

SGMII Transmit Data. 1.25 GBaud input -

Positive and Negative.

Input impedance on the S_IN± pins may be

programmed for 50 ohm or 75 ohm imped-

ance by setting register 26.6. The input

impedance default setting is determined by

the 75/50 OHM configuration pin.

SGMII 625 MHz Receive Clock.

For Serial Interface modes

(HWCFG_MODE[3:0] = 1x00) the S_CLK±

pins become Signal Detect± (SD±) inputs.

SGMII Receive Data. 1.25 GBaud output -

Positive and Negative.

Output impedance on the S_OUT± pins may

be programmed for 50 ohm or 75 ohm

impedance by setting register 26.5. Output

amplitude can be adjusted via register

26.2:0. The output impedance default setting

is determined by the 75/50 OHM configura-

tion pin.

Copyright © 2009 Marvell

March 4, 2009, Advance

Document Classification: Proprietary Information

Doc. No. MV-S105540-00, Rev. --

Page 19

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