AD1881 查看數據表（PDF） - Analog Devices

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AD1881

AC'97 SoundMAX® Codec

Analog Devices 

ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page27

AD1881

Extended Audio Status and Control Register (Index 2Ab)

Reg

Num

Name

lAh ExteDdedAudio StlClrI

D15 D14 D13 D1Z Dll D10 D9 D8 D7 D6 D5 D4 D3 DZ D1 DO Default

X X X X X X X X X X X X X X X VRA Da

Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio

features.

VRA

= Variable Rate Audio. VRA I enables Variable Rate Audio mode (sample rate control registers and SLOTREQ

signaling.

PCM DAC Rate Register (Index 2Ch)

OBSOLETE Reg

Num

ZCh/(7Ah)

Name

DI5 DI4 DB DlZ 011 010 09 08 07 06 05 04 03 02 DI DO Default

PCM DAC Rate SR1S SRl4 SRl3 SR1l SRn SR10 SR9 SR8 SR7 SR6 SRS SR4 SR3 SRZ SRI SRO BB80h

Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ab must be set for the alias to work; if a zero is written to VRA, both sample

rates are reset to 48k.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 7 kHz (lB58h) to 48 kHz (BB80h) in

I Hz increments. Programming a value outside of the range 7040 Hz (I b80h) to 48000 Hz (bb80h) causes the

codec to saturate to 48 kHz if a rate greater than 48 kHz is programmed or to 7 kHz if a rate less than 7 kHz is

programmed. For all rates, if the value written to the register is supported, that value will be echoed back when

read, otherwise the closest rate supported is returned.

PCM ADC Rate Register (Index 32h)

Reg

Name

Hum

015 014 DB Dl2 011 DID 09 08 07 D6 D5 04 03 02 DI DO Default

32h1(78h)PCM ADC Rate SKIS SR14 SRB SRI2 SRn SRIO SR9 SR8 SR7 SR6 SRS SR4 SR3 SR2 SRI SRO BB80h

Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample

rates are reset to 48k.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 7 kHz (lB58h) to 48 kHz (BB80h) in

I Hz increments. Programming a value outside of the range 7040 Hz (lb80h) to 48000 Hz (bb80h) causes the

codec to saturate to 48 kHz if a rate greater than 48 kHz is programmed, or to 7 kHz if a rate less than 7 kHz is

programmed. For all rates, if the value written to the register is supported, that value will be echoed back when

read, otherwise the closest rate supported is returned.

Serial Configuration (Index 74h)

Rex

Num N.....8

D15 DI4

D13

DlZ

Dll

DIU

D9

D8

D7 D6 D5 D4 D3 D

Dl

DO

D..fttult

74h

Serial

SLOT

Configuratio1n 6

REGMZ

REGMI

REGMO

DRQEN DLRQZ

DLRQl

DLRQO X

X

X

X

X

DRRQZ DRRQl DRRQO X

Note: This register is not reset when the reset register (register OOh)is written.

DRRQO

Master Codec DAC right request.

DRRQI

Slave I Codec DAC right request.

DRRQ2

Slave 2 Codec DAC right request.

DLRQO

Master Codec DAC left request.

DLRQI

Slave I Codec DAC left request.

DLRQ2

Slave 2 Codec DAC left request.

DRQEN

Enable DAC request bits in status address and data slot.

REGMO

Master Codec register mask.

REGMI

Slave I Codec register mask.

REGM2

SLOT I 6

Slave 2 Codec register mask.

Enable 16-bit slots.

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REV. 0

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