AD1881 查看數據表（PDF） - Analog Devices

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AD1881

AC'97 SoundMAX® Codec

Analog Devices 

ANALOGDEVICES fAX-ON-DEHAND HOTLINE - Page ~B

AD1881

DRQEN and DxRQx are retained only for compatibility with the AD 1819. New controller designs should use the VRA bit in register

2Ah and the request bits in the status address slot instead.

If your system uses only a single ADI88I, you can ignore the register mask and the slave lIslave 2 request bits. If you write to this

register, write ones to all of the register mask bits. The DxRQx bits are read-only.

The Codec asserts the DxRQx bit when the corresponding DAC channel can accept data in the next frame. These bits are snapshots

of the Codec state taken when the current frame began (effectively, on the rising edge of SYNC), but they also take notice of DAC

samples sent in the current frame.

If you set the DRQEN bit, the ADI881 will fIll all; otherwise, unused AC link status address and data slots with the contents of

register 74h. That makes it somewhat simpler to access the information because you don't need to continually issue AC link read

commands to obtain the register contents.

Also, the DAC requests are reflected in Slot 1, bits (11 . . . 6).

SLOT 16 makes all AC link slots 16 bits in length, formatted into 16 slots.

OBSOLETE i\1iscellaneous Control Bits (Index 76h)

Reg Nmne

Num

015 014 013 012 011 010 09 08 07

76h

MiseControl llits

OAC

Z

(PMl

X

X

OAM OMS OI5R X

ALSR

MOO

EN

06

05 04 03 02

01 00

Oefauh

SRXI0 SRXS

07 07

X

X

ORSR X

ARSR OOOOh

ARSR

DRSR

SRX8D7

SRXIOD7

MODEN

ALSR

ADC right sample generator select

0 = SROSelected(32h)

1 = SRI Selected (2Ch).

DAC right sample generator select

0 = SROSelected (32h)

1 = SRI Selected (2Ch).

Multiply SRI rate by 8/7.

Multiply SRI rate by 10/7. SRXIOD7 and SRXSD7 are mutually exclusive; SRX1OD7 has priority if both are set.

Modem filter enable (left channel only). Change only when DACs are powered down.

ADC left sample generator select

0 = SRO Selected (32h)

1 = SRI Selected (2Ch).

DLSR

DAC left sample generator select

0 = SROSelected (32h)

1 = SRI Selected (2Ch).

DMS

Digital Mono Select.

0 = Mixer

1 = Left DAC and Right DAc.

DAM

Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.

LPMIX

Low Power Mixer. Keeps CD to UNE_Our alive for notebook applications.

DACZ

Zero fIll (vs. repeat) ifDAC is starved-for data.

Sample Rate 0 (Index 78h)

Reg

Nwn

Nmne

015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 Oefaul

78h SatnpleRae 0 SRO15 SRO14 SRO13 SRO12 SROll SROI0 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SROI SROO BB80H

Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both

sample rates are reset to 48k.

SRO[I5:0]

Writing to this register allows the user to program the sampling frequency from 7 kHz (IB58h) to 48 kHz (BB80h)

in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable

results.

REV. 0

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