AD6659 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD6659

Dual IF Receiver

Analog Devices 

AD6659

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK+ 1

CLK– 2

SYNC 3

NC 4

NC 5

NC 6

NC 7

(LSB) D0B 8

D1B 9

DRVDD 10

D2B 11

D3B 12

D4B 13

D5B 14

D6B 15

D7B 16

PIN 1

INDICATOR

AD6659

TOP VIEW

(Not to Scale)

48 PDWN

47 OEB

46 CSB

45 SCLK/DFS

44 SDIO/DCS

43 ORA

42 D11A (MSB)

41 D10A

40 D9A

39 D8A

38 D7A

37 DRVDD

36 D6A

35 D5A

34 D4A

33 D3A

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO

ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL

STRENGTH BENEFITS.

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

0, EP

AGND

1, 2

3

4 to 7, 25 to 27, 29

8, 9, 11 to 18, 20, 21

10, 19, 28, 37

22

23

24

30 to 36, 38 to 42

43

44

CLK+, CLK−

SYNC

NC

D0B to D11B

DRVDD

ORB

DCOB

DCOA

D0A to D11A

ORA

SDIO/DCS

45

SCLK/DFS

46

CSB

47

OEB

48

PDWN

Description

Exposed paddle is the only ground connection for the chip. It must be connected to

the printed circuit board (PCB) AGND.

Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.

Do Not Connect.

Channel B Digital Outputs. D11B is the MSB and D0B is the LSB.

Digital Output Driver Supply (1.8 V to 3.3 V).

Channel B Out-of-Range Digital Output.

Channel B Data Clock Digital Output.

Channel A Data Clock Digital Output.

Channel A Digital Outputs. D11A is the MSB and D0A is the LSB.

Channel A Out-of-Range Digital Output.

SPI Data Input/Output (SDIO). The SDIO function provides bidirectional SPI data I/O in

SPI mode with a 30 kΩ internal pull-down in SPI mode. The duty cycle stabilizer (DCS pin

function) is the static enable input for the duty cycle stabilizer in non-SPI mode with a

30 kΩ internal pull-up in non-SPI (DCS) mode.

SPI Clock (SCLK) Input in SPI Mode/Data Format Select (DFS). 30 kΩ internal pull-down for both

SCLK and DFS. The DFS function provides static control of data output format in non-SPI mode.

When DFS is high, it equals twos complement output. When DFS is low, it equals offset binary

output.

SPI Chip Select. Active low enable; 30 kΩ internal pull-up.

Digital Input. When OEB is low, it enables the Channel A and Channel B digital outputs; when

OEB is high, the outputs are tristated. 30 kΩ internal pull-down.

Digital Input. 30 kΩ internal pull-down. When PDWN is high, it powers down the device.

When PDWN is low, the device runs in normal operation.

Rev. " | Page 10 of 40

Share Link: