AD6659 查看數據表（PDF） - Analog Devices
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AD6659 Datasheet PDF : 40 Pages
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AD6659
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO1/DCS2)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 μA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 μA
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 μA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 μA
Temp Min
Full
Full
0.2
Full
GND − 0.3
Full
−10
Full
−10
Full
8
Full
Full
1.2
Full
0
Full
−50
Full
−10
Full
Full
Full
1.2
Full
0
Full
−10
Full
40
Full
Full
Full
1.2
Full
0
Full
−10
Full
40
Full
Full
Typ
CMOS/LVDS/LVPECL
0.9
10
4
30
2
26
2
26
5
Max
3.6
AVDD + 0.2
+10
+10
12
DRVDD + 0.3
0.8
−75
+10
DRVDD + 0.3
0.8
+10
135
DRVDD + 0.3
0.8
+10
130
Full
3.29
Full
3.25
Full
0.2
Full
0.05
Full
1.79
Full
1.75
Full
0.2
Full
0.05
1 Internal 30 kΩ pull-down.
2 Internal 30 kΩ pull-up.
Unit
V
V p-p
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
V
V
V
V
V
V
Rev. " | Page 6 of 40
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