AD6659 查看數據表（PDF） - Analog Devices
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AD6659 Datasheet PDF : 40 Pages
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AD6659
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
With NSR Enabled
With QEC Enabled
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
Unit
480
3
80
12.5
6.25
1.0
0.1
MHz
MSPS
ns
ns
ns
ps rms
3
ns
3
ns
0.1
ns
9
Cycles
10
Cycles
11
Cycles
350
μs
260
ns
2
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
N–9
N–8
tPD
Figure 2. CMOS Output Data Timing
N–7
N–6
N–5
Rev. " | Page 7 of 40
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