AD6659 查看數據表（PDF） - Analog Devices
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AD6659 Datasheet PDF : 40 Pages
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AD6659
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
CH A CH B CH A CH B CH A
N–9 N–9 N–8 N–8 N–7
tPD
Figure 3. CMOS Interleaved Output Timing
CH B
N–7
CH A
N–6
CH B
N–6
CH A
N–5
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Test Conditions/Comments
SYNC to rising edge of CLK setup time (see Figure 4)
SYNC to rising edge of CLK hold time (see Figure 4)
Setup time between the data and the rising edge of SCLK (see Figure 50)
Hold time between the data and the rising edge of SCLK (see Figure 50)
Period of the SCLK (see Figure 50)
Setup time between CSB and SCLK (see Figure 50)
Hold time between CSB and SCLK (see Figure 50)
SCLK pulse width high (see Figure 50)
SCLK pulse width low (see Figure 50)
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge
Min Typ Max Unit
0.24
ns
0.40
ns
2
ns
2
ns
40
ns
2
ns
2
ns
10
ns
10
ns
10
ns
10
ns
Timing Diagram
CLK+
SYNC
tSSYNC
tHSYNC
Figure 4. SYNC Input Timing Requirements
Rev. " | Page 8 of 40
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