ADF4113HVBCPZ-RL7(Rev0) 查看數據表（PDF） - Analog Devices

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ADF4113HVBCPZ-RL7
(Rev.:Rev0)

High Voltage Charge Pump, PLL Synthesizer

Analog Devices 

ADF4113HV

DEVICE PROGRAMMING AFTER INITIAL

POWER-UP

After initial power-up of the device, there are two ways to

program the device.

CE Pin Method

1. Apply VDD.

2. Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

3. Program the function latch (10). Program the R counter

latch (00). Program the AB counter latch (01).

4. Bring CE high to take the device out of power-down. The R

and AB counters resume counting in close alignment.

After CE goes high, a duration of 1 μs is sometimes required for

the prescaler band gap voltage and oscillator input buffer bias to

reach steady state.

CE can be used to power the device up and down to check for

channel activity. The input register does not need to be repro-

grammed each time the device is disabled and enabled as long

as it has been programmed at least once after VDD was initially

applied.

Counter Reset Method

1. Apply VDD.

2. Conduct a function latch load (10 in 2 LSBs). As part of

this, load 1 to the F1 bit. This enables the counter reset.

3. Conduct an R counter load (00 in 2 LSBs).

4. Conduct an AB counter load (01 in 2 LSBs).

5. Conduct a function latch load (10 in 2 LSBs). As part of

this, load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initiali-

zation method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump, but does not trigger synchronous

power-down.

Rev. 0 | Page 14 of 20

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