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ADM6926 查看數據表(PDF) - Unspecified

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ADM6926 Datasheet PDF : 85 Pages
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ADM6926
Interface Description
Name
M0RXDV
M0RXD
[0:3]
Type
I,
TTL
PD
I,
TTL
PD
M1CRS
M1COL
M1TXD
[0:3]
I,
TTL
PD
I,
TTL
PD
I/O,
TTL
8mA
M1TXEN O, TTL
8mA
PU
M1TXCLK I,
TTL
PD
M1RXCLK I,
TTL
PD
M1RXDV I,
TTL
PD
M1RXD I,
[0:3]
TTL
PD
Pin #
77
80,81,82,
83
84
85
89,88,87,
86
92
93
94
95
96,97,98,
99
Description
MII Port 0 Receive Data Valid.
RMII Port 0 Carrier Sense/Receive Data Valid.
This pin is internal pull_down.
MII Port 0 Receive Data Bit[0:3].
RMII Port 0 Receive Data Bit[0:1].
If in RMII mode, M0RXD[3] used for ext_dup_enable and
M0RXD[2] used for ext_dup_full. Internal pull_down. See
Sec3.1.27 for details.
MII Port 1 Carrier Sense
This pin is internal pull_down.
MII Port 1 Collision input
This pin is internal pull_down.
MII Port 1Transmit Data Bit[0:3].
Synchronous to the rising edge of M1TXCLK.
RMII Port 1Transmit Data Bit[0:1].
Synchronous to the rising edge of M1RXCLK.
BPEN. Value on M1TXD[3] will be latched at the rising
edge of RESETL to set Back_pressure enable. Internal
pull_up.
FCEN. Value on M1TXD[2] will be latched at the rising
edge of RESETL to set flow control enable. Internal pull_up.
TNKEN. Value on M1TXD[1] will be latched at the rising
edge of RESETL to set trunking enable. Internal pull_up.
IPGLVING. Value on M1TXD[0] will be latched at the
rising edge of RESETL to set shorter IPG. Internal
pull_down.
MII Port 1 Transmit Enable.
ANEN. Value on this pin will be latched at the rising edge of
RESETL to set auto_negotiation enable. Internal pull_up.
MII Port1 Transmit clock Input. This signal is 25MHz
input for MII interface.
MII1 Receive Clock Input. This signal is 25MHz input for
MII interface and 50MHz REFCLK input for RMII interface.
MII/RMII Port 1 Receive Data Valid.
This pin is internal pull_down.
MII Port 1 Receive Data Bit[0:3].
RMII Port 1 Receive Data Bit[0:1].
If in RMII mode, M1RXD[3] used for ext_dup_enable and
M1RXD[2] used for ext_dup_full. Internal pull_down. See
Sec3.1.27 for details.
ADMtek Inc.
2-4

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