ADM6926 查看數據表（PDF） - Unspecified

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产品描述 (功能)

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ADM6926

26 port 10/100 Mbps Ethernet Switch Controller

Unspecified 

ADM6926

Interface Description

2.2.3 Power/Ground

Pin Name Pin Type Pin #

Pin Description

GNDRG Analog 12

Ground

Ground for Regulator

VCCRG

GNDPLL

Analog 11

Power

Analog 16

Ground

3.3V Power supply for Regulator

Ground for PLL

VCCPLL

GNDIK

Analog 15

1.8V Power supply PLL

Power

Digital 35,50,67, Ground for Core Logic

Ground 91,122

VCCIK

Digital 34,49,66, 1.8V Power supply for Core Logic

Power 90,121

GNDO

Digital 1,29,52, Ground for I/O PAD

Ground 79,111

VCC3O

Digital 28,51,78, 3.3V Power supply for I/O PAD

Power 110,128

2.2.4 Miscellaneous pins, 16 pins

Pin Name Pin Type Pin #

Pin Description

CK25MO O, TTL 7

25MHz clock Output. This pin will drive out 25Mhz.

16mA

CK50MO/ O, TTL 5

COL_LED_ 16mA

50MHz clock Output. This pin will drive out 50MHz.

COL_LED_10M. This pin shows collision LED for 10M

10M

domain (see EEPROM Register 1ch, Bit[9])

XI

I,

22

Crystal or OSC 50MHz Input. This is the clock source of

Analog

PLL. The PLL will generate 125Mhz for SS-SMII and

50MHz for RMII and 25Mhz for MII.

XO

O,

23

Crystal 50Mhz Output.

Analog

RESETL I, TTL 59

Reset Signal. An active low signal with minimum 100ms

SCHE

duration is required.

ALERT/ O, TTL 103

Alert LED Display. This pin will show the status of power-

COL_LED_ 8mA

100M

on-diagnostic and broadcast traffic.

COL_LED_100M. This pin shows collision LED for 100M

domain (see EEPROM Register 1ch, Bit[9])

TEST[2:1] I,

21,24 Industrial Test pins.

TTL

These pins are internal pull_down.

PD

MDC

O, TTL 19

Management Data Clock.

16mA

This pin output 2.2MHz clock to drive PHY and access

corresponding speed and duplex and link status through

ADMtek Inc.

2-5

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