ADN2817ACPZ-RL7(RevG) 查看數據表（PDF） - Analog Devices
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ADN2817ACPZ-RL7
(Rev.:RevG)
(Rev.:RevG)
Analog Devices
ADN2817ACPZ-RL7 Datasheet PDF : 38 Pages
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ADN2817/ADN2818
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN,
DATAOUTP/DATAOUTN)
Single-Ended Output Swing, VSE
Differential Output Swing, VDIFF
Output Voltage
High, VOH
Low, VOL
CML Outputs Timing
Rise Time
Fall Time
Setup Time, tS
Hold Time, tH
Setup Time, tDDRS
Hold Time, tDDRH
I2C INTERFACE DC CHARACTERISTICS
Input Voltage
High, VIH
Low, VIL
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
High, tHIGH
Low, tLOW
Start Condition
Hold Time, tHD;STA
Setup Time, tSU;STA
Data
Setup Time, tSU;DAT
Hold Time, tHD;DAT
SCK/SDA Rise/Fall Time, tR/tF
Stop Condition Setup Time, tSU;STO
Bus Free Time Between a Stop and a Start, tBUF
REFCLK CHARACTERISTICS
Input Voltage Range
VIL
VIH
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
Data Sheet
Test Conditions/Comments Min
Typ
Max
Unit
See Figure 3
See Figure 3
300
350
600
mV
600
700
1200
mV
VCC
V
VCC − 0.6 VCC − 0.35 VCC − 0.3 V
20% to 80%
80% to 20%
See Figure 2, OC-48
See Figure 2, OC-48
See Figure 4, OC-48
See Figure 4, OC-48
LVCMOS
80
112
ps
80
123
ps
150
200
250
ps
150
200
250
ps
140
170
200
ps
200
230
260
ps
0.7 VCC
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 22
−10.0
V
0.3 VCC V
+10.0
µA
0.4
V
400
kHz
600
ns
1300
ns
600
ns
600
ns
Optional lock to REFCLK mode
At REFCLKP or REFCLKN
100
300
20 + 0.1 Cb
600
1300
0
VCC
100
10
100
ns
ns
300
ns
ns
ns
V
V
mV p-p
200
MHz
ppm
Rev. G | Page 6 of 38
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