ADSP-21261 查看數據表（PDF） - Analog Devices
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ADSP-21261 Datasheet PDF : 48 Pages
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ADSP-21261/ADSP-21262/ADSP-21266
Clock Input
See Table 16 and Figure 6.
Table 16. Clock Input
Parameter
150 MHz1
Min
Max
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
203
1604
7.53
804
7.53
804
tCKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
3
fvco5
VCO Frequency
200
800
tCCLK
CCLK Period6
6.66
10
1 Applies to all 150 MHz models. See Ordering Guide on Page 45.
2 Applies to all 200 MHz models. See Ordering Guide on Page 45.
3 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
4 Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
5 See Figure 4 on Page 16 for VCO diagram.
6 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
Min
153
63
63
200
5
200 MHz2
Max
1604
804
804
3
800
10
CLKIN
tCKH
tCK
tCKL
Figure 6. Clock Input
Clock Signals
The ADSP-2126x can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-2126x to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL. Figure 7 shows
the component connections used for a crystal operating in fun-
damental mode. Note that the 200 MHz clock rate is achieved
using a 12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
CLKIN
1M ⍀
XTAL
C1
X1
C2
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
Figure 7. 150 MHz or 200 MHz Operation with a 12.5 MHz
Fundamental Mode Crystal
Rev. G | Page 18 of 48 | December 2012
Unit
ns
ns
ns
ns
MHz
ns
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