ADSP-21261 查看數據表（PDF） - Analog Devices

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ADSP-21261

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

Reset

See Table 17 and Figure 8.

Table 17. Reset

Parameter

Min

Max

Unit

Timing Requirements

tWRST

RESET Pulse Width Low1

4  tCK

ns

tSRST

RESET Setup Before CLKIN Low

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST

tSRST

Figure 8. Reset

Interrupts

The timing specification in Table 18 and Figure 9 applies to the

FLAG0, FLAG1, and FLAG2 pins when they are configured as

IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1

pins when configured as interrupts.

Table 18. Interrupts

Parameter

Timing Requirements

tIPW

IRQx Pulse Width

Min

2 tCCLK +2

Max

Unit

ns

INTERRUPT

INPUTS

tIPW

Figure 9. Interrupts

Rev. G | Page 19 of 48 | December 2012

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