ADSP-21261 查看數據表（PDF） - Analog Devices

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ADSP-21261

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

Core Timer

The timing specification in Table 19 and Figure 10 applies to

FLAG3 when it is configured as the core timer (CTIMER).

Table 19. Core Timer

Parameter

Switching Characteristics

tWCTIM

CTIMER Pulse Width

Min

4 × tCCLK – 1

Max

Unit

ns

FLAG3

(CTIMER)

tWCTIM

Figure 10. Core Timer

Timer PWM_OUT Cycle Timing

The timing specification in Table 20 and Figure 11 applies to

Timer in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DAI_P20–1 pins through the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 20. Timer PWM_OUT Timing

Parameter

Switching Characteristics

tPWMO

Timer Pulse Width Output

Min

2  tCCLK – 1

Max

2(231 – 1)  tCCLK

Unit

ns

PWM

OUTPUTS

tPWMO

Figure 11. Timer PWM_OUT Timing

Rev. G | Page 20 of 48 | December 2012

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