AS1160 查看數據表（PDF） - austriamicrosystems AG

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AS1160

20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

austriamicrosystems AG 

AS1160/AS1161

Datasheet - Timing Diagrams

Figure 18. Serializer Bus LVDS Output Load and Transition Times

DO+

DO-

VDIFF = DO+ - DO-

RLOAD

28Ω

10pF 10pF

VDIFF

80%

20%

tLLHT

Figure 19. Deserializer CMOS/TTL Output Load and Transition Times

Deserializer

CMOS/TTL

Output

15pF

80%

20%

tCLH

80%

VDIFF = 0V

20%

tLHLT

80%

20%

tCHL

Figure 20. Serializer Input Clock Transition Time

TCLK

90%

10%

tCLKT

Figure 21. Serializer Setup and Hold Times

TCLK

3V

90%

10%

0V

tCLKT

1.5V

tTCP

1.5V

1.5V

DIN0:9

Setup

tDIS

1.5V

tDIH

Hold

1.5V

Timing shown for TCKR/FN is low

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

13 - 29

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