AS1160 查看數據表（PDF） - austriamicrosystems AG

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AS1160

20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

austriamicrosystems AG 

AS1160/AS1161

Datasheet - Timing Diagrams

Figure 22. Serializer Tri-State Test Circuit and Timing

DEN

DO+

DO-

RLOAD

28Ω

10pF 10pF

3V

DEN

0V

VOH

DO+

DO-

VOL

1.5V

tHZD

50%

tLZD

50%

1.5V

tZHD

tZLD

50%

50%

Figure 23. Serializer Power Up Timing

VDD

PWDNN

tPWDL

Figure 24. Serializer PLL Lock Time and PWDNN Tri-State Delays

PWDNN

2.0V

TCLK

DO+

DO-

<400 Cycles

...

tPLD

Tri-State

...

tZHD or tZLD

Output

Active

0.8V

tHZD or tLZD

Tri-State

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

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