C8051F063 查看數據表（PDF） - Silicon Laboratories

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C8051F063

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

Figure 24.6. CKCON: Clock Control Register ........................................................ 293

Figure 24.7. TL0: Timer 0 Low Byte ....................................................................... 294

Figure 24.8. TL1: Timer 1 Low Byte ....................................................................... 294

Figure 24.9. TH0: Timer 0 High Byte...................................................................... 294

Figure 24.10. TH1: Timer 1 High Byte.................................................................... 294

Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram ...................................... 296

Figure 24.12. T2, 3, and 4 Auto-reload Mode Block Diagram ................................ 297

Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers ................................ 299

Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers ....................... 300

Figure 24.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte .................. 301

Figure 24.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte................. 301

Figure 24.17. TMRnL: Timer 2, 3, and 4 Low Byte................................................. 301

Figure 24.18. TMRnH: Timer 2, 3, and 4 High Byte ............................................... 302

25. Programmable Counter Array ............................................................................. 303

Figure 25.1. PCA Block Diagram............................................................................ 303

Figure 25.2. PCA Counter/Timer Block Diagram.................................................... 304

Figure 25.3. PCA Interrupt Block Diagram ............................................................. 305

Figure 25.4. PCA Capture Mode Diagram.............................................................. 306

Figure 25.5. PCA Software Timer Mode Diagram .................................................. 307

Figure 25.6. PCA High Speed Output Mode Diagram............................................ 308

Figure 25.7. PCA Frequency Output Mode ............................................................ 309

Figure 25.8. PCA 8-Bit PWM Mode Diagram ......................................................... 310

Figure 25.9. PCA 16-Bit PWM Mode...................................................................... 311

Figure 25.10. PCA0CN: PCA Control Register ...................................................... 312

Figure 25.11. PCA0MD: PCA0 Mode Register....................................................... 313

Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers................... 314

Figure 25.13. PCA0L: PCA0 Counter/Timer Low Byte........................................... 315

Figure 25.14. PCA0H: PCA0 Counter/Timer High Byte ......................................... 315

Figure 25.15. PCA0CPLn: PCA0 Capture Module Low Byte ................................. 316

Figure 25.16. PCA0CPHn: PCA0 Capture Module High Byte................................ 316

26. JTAG (IEEE 1149.1) .............................................................................................. 317

Figure 26.1. IR: JTAG Instruction Register............................................................. 317

Figure 26.2. DEVICEID: JTAG Device ID Register ................................................ 321

Figure 26.3. FLASHCON: JTAG Flash Control Register........................................ 323

Figure 26.4. FLASHDAT: JTAG Flash Data Register............................................. 324

Figure 26.5. FLASHADR: JTAG Flash Address Register....................................... 324

27. Document Change List ........................................................................................ 327

Rev. 1.2

15

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