C8051F063 查看數據表（PDF） - Silicon Laboratories

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C8051F063

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

Table 19.1.CAN Register Index and Reset Values ............................................... 229

20. System Management BUS / I2C BUS (SMBUS0) ............................................... 235

Table 20.1.SMB0STA Status Codes and States ................................................... 248

21. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 251

Table 21.1.SPI Slave Timing Parameters ............................................................. 264

22. UART0 ................................................................................................................... 265

Table 22.1.UART0 Modes ..................................................................................... 266

Table 22.2.Oscillator Frequencies for Standard Baud Rates ................................ 273

23. UART1 ................................................................................................................... 277

Table 23.1.Timer Settings for Standard Baud Rates Using the Internal Oscillator 284

Table 23.2.Timer Settings for Standard Baud Rates Using an External Oscillator 284

Table 23.3.Timer Settings for Standard Baud Rates Using an External Oscillator 285

Table 23.4.Timer Settings for Standard Baud Rates Using an External Oscillator 285

Table 23.5.Timer Settings for Standard Baud Rates Using an External Oscillator 286

Table 23.6.Timer Settings for Standard Baud Rates Using an External Oscillator 286

24. Timers ................................................................................................................... 287

25. Programmable Counter Array ............................................................................ 303

Table 25.1.PCA Timebase Input Options .............................................................. 304

Table 25.2.PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 305

26. JTAG (IEEE 1149.1) ............................................................................................. 317

Table 26.1.Boundary Data Register Bit Definitions (C8051F060/2/4/6) ................ 318

Table 26.2.Boundary Data Register Bit Definitions (C8051F061/3/5/7) ................ 320

27. Document Change List ....................................................................................... 327

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Rev. 1.2

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