GS8170DW18C-300I 查看數據表（PDF） - Giga Semiconductor
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GS8170DW18C-300I Datasheet PDF : 36 Pages
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Preliminary
GS8170DW18/36/72C-333/300/250
Programmable Enables
ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, PE2 and PE3. For example, if PE2 is held at VDD,
E2 functions as an active high enable. If PE2 is held to VSS, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four ΣRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
ΣRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic
A0–An
E1
CK
W
DQ0–DQn
A0–An – 2
An – 1
An
CQ
Bank 0
A
A0–An – 2
E3
An – 1
E2
An
E1
CK
W EP3 0
DQ EP2 0
CQ
Bank 1
A
E3
E2
A0–An – 2
An – 1
An
E1
CK
W EP3 1
DQ EP2 0
CQ
Bank 2
A
E3
E2
A0–An – 2
An – 1
An
E1
CK
W EP3 0
DQ EP2 1
CQ
Bank Enable Truth Table
EP2
EP3
Bank 0
VSS
VSS
Bank 1
VSS
VDD
Bank 2
VDD
VSS
Bank 3
VDD
VDD
E2
Active Low
Active Low
Active High
Active High
E3
Active Low
Active High
Active Low
Active High
Bank 3
A
E3
E2
E1
CK
W EP3 1
DQ EP2 1
CQ
Rev: 1.00d 6/2002
15/36
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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