GS8170DW18C-300I 查看數據表（PDF） - Giga Semiconductor

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GS8170DW18C-300I

18Mb Σ1x1 Double Late Write SigmaRAM™ SRAM

Giga Semiconductor 

.

CK

Address

ADV

/E1

/E2 Bank 1

E2 Bank 2

DQ

Bank 1

CQ

Bank 1

Read

A

Preliminary

GS8170DW18/36/72C-333/300/250

Pipelined Read Bank Switch with E1 Deselect

No Op

Read

Read

Read

XX

C

D

E

F

QA

CQ1 + CQ2

CQ

Bank 2

DQ

Bank 2

QC

QD

Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

FLXDrive™ Output Driver Impedance Control

The ZQ pin allows selection between ΣRAM nominal drive strength (ZQ floating or low) for multi-drop bus applications and low

drive strength (ZQ high) point-to-point applications.

Rev: 1.00d 6/2002

17/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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