GS8170DW18C-300I 查看數據表（PDF） - Giga Semiconductor

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GS8170DW18C-300I

18Mb Σ1x1 Double Late Write SigmaRAM™ SRAM

Giga Semiconductor 

Common I/O State Diagram

0,T,0,1

X,F,0,X or X,X,1,X

Bank

Deselect

1,T,0,X

Preliminary

GS8170DW18/36/72C-333/300/250

0,T,0,0

X,F,0,X

Deselect

0,T,0,1

0,T,0,0

1,T,0,X or X,X,1,X

1,T,0,X

X,F,0,X

Read

0,T,0,0

0,T,0,1

1,T,0,X

Write

X,F,0,X

0,T,0,1

X,X,1,X

X,X,1,X

0,T,0,0

1,T,0,X

X,F,0,X

0,T,0,1

Read

Continue

0,T,0,0 0,T,0,1

0,T,0,0

Write

Continue

1,T,0,X

X,F,0,X

X,X,1,X

n

Key

Input Command Code

Clock (CK)

ƒ Transition

Current State (n)

Next State (n + 1)

Command

X,X,1,X

n+1

n+2

n+3

ƒ

ƒ

ƒ

ƒ

Current State

Next State

Current State & Next State Definition for Read/Write Control State Diagram

Notes:

1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W, respectively.

2. If (E2 = EP2 and E3 = EP3), then E = “T” else E = “F”.

3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

Rev: 1.00d 6/2002

19/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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