CXA2153S 查看數據表（PDF） - Sony Semiconductor

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CXA2153S

Preamplifier for High Resolution Computer Display

Sony Semiconductor 

CXA2153S

I2C BUS Register Definitions

Slave Address

SLAVE RECEIVER: 40 (HEX)

Register Table

Sub Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

BIT 7

∗

POL1

∗

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

CONTRAST

BRIGHTNESS

R_BKG

G_BKG

B_BKG

OSD GAIN

G2

R_DRV

G_DRV

B_DRV

∗

SHP WIDTH

SHP GAIN

GAMMA1

POL2

GAMMA2

∗

VDET LVL VDET OFF SOG OFF GAM OFF

0

BIT 0

D R OFF

∗: Don't Care

Sub Address 0000 CONTRAST (8)

Controls the gain common to the R, G and B channels. Since control is

performed by multiplying with R/G/B DRIVE, the white balance can be

adjusted by R/G/B DRIVE and the luminance can be adjusted by

CONTRAST.

0: Output level minimum (0Vp-p)

255: Output level maximum (4.4Vp-p; with 0.7Vp-p input)

Sub Address 0001 BRIGHTNESS (8) Controls the black level common to the R, G and B channels.

0: Black level minimum (0.8V)

255: Black level maximum (2.9V)

Sub Address 0010 R_BKG (8)

Controls Pin 21 (R BACKGROUND) output voltage.

0: Output voltage minimum (1.5V)

255: Output voltage maximum (5.5V)

Sub Address 0011 G_BKG (8)

Controls Pin 20 (G BACKGROUND) output voltage.

0: Output voltage minimum (1.5V)

255: Output voltage maximum (5.5V)

Sub Address 0100 B_BKG (8)

Controls Pin 19 (B BACKGROUND) output voltage.

0: Output voltage minimum (1.5V)

255: Output voltage maximum (5.5V)

–8–

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