CXA2153S 查看數據表（PDF） - Sony Semiconductor

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CXA2153S

Preamplifier for High Resolution Computer Display

Sony Semiconductor 

CXA2153S

Sub Address 0101 OSD GAIN (8)

Controls the OSD gain common to the R, G and B channels. Since

control is performed by multiplying with R/G/B DRIVE, the video white

balance and tracking are obtained.

0: Gain minimum (0Vp-p)

255: Gain maximum (4.5Vp-p)

Sub Address 0110 G2 (8)

Controls Pin 18 (G2) output voltage.

0: Output voltage minimum (1.5V)

255: Output voltage maximum (5.5V)

Sub Address 0111 R_DRV (8)

Controls the gain for the R channel. Control is performed by multiplying

with CONTRAST. Use this for adjusting the white balance.

0: Output level minimum (0Vp-p)

255: Output level maximum (4.4Vp-p; with 0.7Vp-p input)

Sub Address 1000 G_DRV (8)

Controls the gain for the G channel. Control is performed by multiplying

with CONTRAST. Use this for adjusting the white balance.

0: Output level minimum (0Vp-p)

255: Output level maximum (4.4Vp-p; with 0.7Vp-p input)

Sub Address 1001 B_DRV (8)

Controls the gain for the B channel. Control is performed by multiplying

with CONTRAST. Use this for adjusting the white balance.

0: Output level minimum (0Vp-p)

255: Output level maximum (4.4Vp-p; with 0.7Vp-p input)

Sub Address 1010 SHP WIDTH (2)

Controls the sharpness time constant switching.

0: OFF

1: 25ns

2: 50ns

3: 100ns

Sub Address 1010 SHP GAIN (4)

Controls the sharpness gain.

0: Gain minimum (0dB)

F: Gain maximum (6dB) ∗ Amplitude at SHP OFF is assumed to be 0dB.

Sub Address 1011 POL1 (1)

Controls the polarity of the correction at GAMMA1.

0: – correction

1: + correction

Sub Address 1011 GAMMA1 (2)

Controls the gain of the inflection point 1 (15 IRE) at GAMMA.

0: 0 IRE correction

3: 9 IRE correction

Sub Address 1011 POL2 (1)

Controls the polarity of the correction at GAMMA2.

0: – correction

1: + correction

–9–

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