A386DX 查看數據表（PDF） - Intel

零件编号

产品描述 (功能)

生产厂家

A386DX

32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT

Intel 

Intel386TM DX MICROPROCESSOR

Table 2-5 Interrupt Vector Assignments

Function

Interrupt

Number

Instruction Which

Can Cause

Exception

Return Address

Points to

Faulting

Instruction

Type

Divide Error

0

DIV IDIV

YES

FAULT

Debug Exception

1

any instruction

YES

TRAP

NMI Interrupt

2

INT 2 or NMI

NO

NMI

One Byte Interrupt

3

INT

NO

TRAP

Interrupt on Overflow

4

INTO

NO

TRAP

Array Bounds Check

5

BOUND

YES

FAULT

Invalid OP-Code

6

Any Illegal Instruction

YES

FAULT

Device Not Available

7

ESC WAIT

YES

FAULT

Double Fault

8

Any Instruction That Can

Generate an Exception

ABORT

Coprocessor Segment Overrun

9

ESC

NO

ABORT

Invalid TSS

10 JMP CALL IRET INT

YES

FAULT

Segment Not Present

11 Segment Register Instructions

YES

FAULT

Stack Fault

12 Stack References

YES

FAULT

General Protection Fault

13 Any Memory Reference

YES

FAULT

Intel Reserved

15

Page Fault

14 Any Memory Access or Code Fetch

YES

FAULT

Coprocessor Error

16 ESC WAIT

YES

FAULT

Intel Reserved

17 – 31

Two Byte Interrupt

0–255 INT n

NO

TRAP

Some debug exceptions may report both traps on the previous instruction and faults on the next instruction

string moves) When an interrupt occurs the proces-

sor reads an 8-bit vector supplied by the hardware

which identifies the source of the interrupt (one of

224 user defined interrupts) The exact nature of the

interrupt sequence is discussed in section 5

The IF bit in the EFLAG registers is reset when an

interrupt is being serviced This effectively disables

servicing additional interrupts during an interrupt

service routine However the IF may be set explicitly

by the interrupt handler to allow the nesting of inter-

rupts When an IRET instruction is executed the

original state of the IF is restored

input is pulled high it causes an interrupt with an

internally supplied vector value of 2 Unlike a normal

hardware interrupt no interrupt acknowledgment se-

quence is performed for an NMI

While executing the NMI servicing procedure the In-

tel386 DX will not service further NMI requests until

an interrupt return (IRET) instruction is executed or

the processor is reset If NMI occurs while currently

servicing an NMI its presence will be saved for serv-

icing after executing the first IRET instruction The IF

bit is cleared at the beginning of an NMI interrupt to

inhibit further INTR interrupts

2 9 4 Non-Maskable Interrupt

Non-maskable interrupts provide a method of servic-

ing very high priority interrupts A common example

of the use of a non-maskable interrupt (NMI) would

be to activate a power failure routine When the NMI

2 9 5 Software Interrupts

A third type of interrupt exception for the Intel386

DX is the software interrupt An INT n instruction

causes the processor to execute the interrupt serv-

ice routine pointed to by the nth vector in the inter-

rupt table

25

Share Link: