A386DX 查看數據表（PDF） - Intel
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A386DX Datasheet PDF : 139 Pages
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Intel386TM DX MICROPROCESSOR
31
16 15
0
BREAKPOINT 0 LINEAR ADDRESS
BREAKPOINT 1 LINEAR ADDRESS
BREAKPOINT 2 LINEAR ADDRESS
BREAKPOINT 3 LINEAR ADDRESS
Intel reserved Do not define
Intel reserved Do not define
0
B
T
B
S
B
D
0
0
0
0
0
0
0
0
0
B
3
B
2
B
1
B
0
LEN
3
RW
33
LEN
2
RW
22
LEN
1
RW
11
LEN
0
RW
00
0
0
G
D
0
0
0
G
E
L
E
G
3
L
3
G
2
L
2
G
1
L
1
G
0
L
0
31
16 15
0
NOTE 0 indicates Intel reserved Do not define SEE SECTION 2 3 10
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
Figure 2-13 Debug Registers
tion breakpoints must have a length of 1 (LENi e
00) Encoding of the LENi field is as follows
LENi
Encoding
00
01
10
11
Breakpoint
Field Width
1 byte
2 bytes
Undefined
do not use
this encoding
4 bytes
Usage of Least
Significant Bits in
Breakpoint Address
Register i (ie0b3)
All 32-bits used to
specify a single-byte
breakpoint field
A1–A31 used to
specify a two-byte
word-aligned
breakpoint field A0 in
Breakpoint Address
Register is not used
A2–A31 used to
specify a four-byte
dword-aligned
breakpoint field A0
and A1 in Breakpoint
Address Register are
not used
The LENi field controls the size of breakpoint field i
by controlling whether all low-order linear address
bits in the breakpoint address register are used to
detect the breakpoint event Therefore all break-
point fields are aligned 2-byte breakpoint fields be-
gin on Word boundaries and 4-byte breakpoint
fields begin on Dword boundaries
The following is an example of various size break-
point fields Assume the breakpoint linear address in
DR2 is 00000005H In that situation the following
illustration indicates the region of the breakpoint
field for lengths of 1 2 or 4 bytes
DR2e00000005H LEN2 e 00B
31
0
bkpt fld2
00000008H
00000004H
00000000H
DR2e00000005H LEN2 e 01B
31
0
00000008H
w x bkpt fld2 00000004H
00000000H
DR2e00000005H LEN2 e 11B
31
0
w bkpt fld2 x
00000008H
00000004H
00000000H
30
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