7C1325B-100 查看數據表（PDF） - Cypress Semiconductor

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7C1325B-100

256K x 18 Synchronous 3.3V Cache RAM

Cypress Semiconductor 

Timing Diagrams (continued)

Read Cycle Timing[14, 16]

CY7C1325B

CLK

Single Read

tCYC

tCH

Burst Read

Unselected

Pipelined Read

tADS

tADH

tCL

ADSP ignored with CE1 inactive

ADSP

tADS

ADSC

ADV

tADVS

tADH

tAS

tADVH

ADD

RD1

RD2

tAH

GW

tWS

tWH

WE

CE1

tCES tCEH

ADSC initiated read

Suspend Burst

RD3

tWS

tWH

CE1 masks ADSP

CE2

tCES

CE3

tCES

OE

Data Out

Unselected with CE2

tCEH

tCEH

tEOV

tOEHZ

tCDV

11aa

tCLZ

tDOH

2a

2b

= DON’T CARE

2c 2c

2d

= UNDEFINED

3a

tCHZ

Note:

16. RDx stands for Read Data from Address X.

11

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