Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 5. Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test Min
[1]
Typ
Max
Unit
SFDRRBW restricted
fdata = 245.76 MHz;
-
bandwidth
fs = 983.04 Msps;
spurious-free fo = 150 MHz
dynamic range
BW = 100 MHz
-
BW = 180 MHz
-
IMD3
third-order
fdata = 245.76 MHz;
C
-
intermodulation fs = 983.04 Msps;
distortion
fo1 = 20 MHz;
fo2 = 21 MHz;
4 interpolation;
output level = 1 dBFS
fdata = 245.76 MHz;
I
-
fs = 983.04 Msps;
fo1 = 152 MHz;
fo2 = 155.1 MHz;
4 interpolation;
output level = 1 dBFS
ACPR
adjacent
WCDMA pattern;
channel power
ratio
fs = 983.04 Msps;
4 interpolation;
fNCO = 153.6 MHz
1 carrier; BW = 5 MHz C
-
2 carriers; BW = 10 MHz C
-
4 carriers; BW = 20 MHz C
-
NSD
noise spectral fs = 983.04 Msps;
D
-
density
4 interpolation;
fo = 20 MHz at 1 dBFS
fs = 983.04 Msps;
D
-
4 interpolation;
fo = 153.6 MHz at 1 dBFS
-
78
-
78
-
75
-
75
-
73
-
70
-
68
-
158
-
155
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] Connect VDDA(1V8)_D, VDDA(1V8)_P1 and VDDA(1V8)_P2 to the same 1.8 V analog power supply. Use dedicated filters for the three power
pins.
[3] Vgpd represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the
inductance between the receiver and the driver circuit ground voltages.
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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