DAC1617D1G0HN 查看數據表（PDF） - Integrated Device Technology

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DAC1617D1G0HN

Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology 

Integrated Device Technology

DAC1617D1G0

Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating

Table 9. Input LVDS bus swapping

Internal LVDS bus

External LVDS bus

(WORD_SWAP = 0)

LDI[15]P,N

LD[15]P,N

LDI[14]P,N

LD[14]P,N

LDI[13]P,N

LD[13]P,N

LDI[12]P,N

LD[12]P,N

LDI[11]P,N

LD[11]P,N

LDI[10]P,N

LD[10]P,N

LDI[9]P,N

LD[9]P,N

LDI[8]P,N

LD[8]P,N

LDI[7]P,N

LD[7]P,N

LDI[6]P,N

LD[6]P,N

LDI[5]P,N

LD[5]P,N

LDI[4]P,N

LD[4]P,N

LDI[3]P,N

LD[3]P,N

LDI[2]P,N

LD[2]P,N

LDI[1]P,N

LD[1]P,N

LDI[0]P,N

LD[0]P,N

External LVDS bus

(WORD_SWAP = 1)

LD[0]P,N

LD[1]P,N

LD[2]P,N

LD[3]P,N

LD[4]P,N

LD[5]P,N

LD[6]P,N

LD[7]P,N

LD[8]P,N

LD[9]P,N

LD[10]P,N

LD[11]P,N

LD[12]P,N

LD[13]P,N

LD[14]P,N

LD[15]P,N

10.4.3 Input port swapping

The LVDS DDR receiver block internally maps the incoming LVDS data bus into two

buses with a single data rate (Figure 7).

A0

A1

A2

A3

A0 B0 A1 B1 A2 B2 A3 B3

PA[15..0]

LD[15..0]P/N

to DAC A

LVDS

RECEIVER

B0

PB[15..0]

LCLKP/N

LCLK

Fig 7. LVDS DDR receiver mapping LDAB SWAP = 0

B1

B2

B3

to DAC B

001aan393

These two buses can be swapped internally using bit LDAB_SWAP of register

LD_CNTRL (see Table 60 and Figure 8).

DAC1617D1G0 3

Preliminary data sheet

Rev. 03 — 2 July 2012

© IDT 2012. All rights reserved.

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