DAC1617D1G0HN 查看數據表（PDF） - Integrated Device Technology

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DAC1617D1G0HN

Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology 

Integrated Device Technology

DAC1617D1G0

Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating

SPI bus

WRITE DAC CONFIGURATION

START CLOCK CALIBRATION

RESET_N

power supplies

ton trst

power in

specification

range

Fig 5. Power-on sequence

tspi_start

time

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10.4 LVDS Data Input Format (DIF) block

The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus

with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of

100 , so an external resistor is not required. The DIF block includes two subblocks:

• LVDS receiver:

Provides high flexibility for the LVDS interface, especially for the PCB layout and the

control of the input port polarity and the input port mapping.

• Data format block:

Enables the adaptation, which ensures the support of several data encoding modes.

LD[15]P

LD[15]N

16 PA[15..0]

16 I[15..0] to DAC A

LD[0]P

LD[0]N

LVDS 16 PB[15..0]

RECEIVER

DATA 16 Q[15..0]

FORMAT

to DAC B

LCLKP

LCLKN

LCLK

Fig 6. LVDS Data Input Format (DIF) block diagram

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10.4.1 Input port polarity

The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can

be changed. This ensures a much easier PCB layout design. The input polarity is

controlled with bits LD_POL[15:0] (see Table 59).

10.4.2 Input port mapping

Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in

register LD_CNTRL (see Table 60) also simplifies the design of the PCB (see Table 9).

DAC1617D1G0 3

Preliminary data sheet

Rev. 03 — 2 July 2012

© IDT 2012. All rights reserved.

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