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DAC1617D1G0HN 查看數據表(PDF) - Integrated Device Technology

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DAC1617D1G0HN Datasheet PDF : 78 Pages
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Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 5. Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test Min
[1]
Typ
Max
Unit
Digital inputs/outputs (pins MDSN, MDSP)
Vo(dif)(p-p)
peak-to-peak
differential
output voltage
C
-
Ci
input
between GND and pin
D
-
capacitance
MDSN or MDSP
Ri
input resistance
Vi
input voltage
Vgpd< 50 mV[3]
Vidth
input differential Vgpd< 50 mV[3]
threshold
voltage
D
-
C
825
C
100
Digital inputs/outputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N, IO0, IO1)
VIL
LOW-level input
voltage
C
GND
VIH
HIGH-level
input voltage
C
0.7VDDD(1V8)
VOL
LOW-level
pins IO0, IO1, SDO and C
GND
output voltage SDIO
VOH
HIGH-level
pins IO0, IO1, SDO and C
0.9VDDD(1V8)
output voltage SDIO
IIL
LOW-level input maximum VIL
current
I
10
IIH
HIGH-level
maximum VIL
input current
I
10
Ci
input
capacitance
D
-
Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN)
Ibias
bias current
DC current
D
-
IO(fs)
full-scale output controlled by the analog D
8.1
current
GAIN registers
(see Table 32)
default value
D
-
VO
VO(cm)
output voltage compliance range
D
2.3
common-mode 1 V (p-p) DAC output
D
-
output voltage 2 V (p-p) DAC output
-
Ro
output
resistance
D
-
Co
output
between pins OUTAN and D
-
capacitance
OUTBN and pins OUTBN
and OUTBP
EO
offset error
variation
D
-
500
0.6
100
-
-
-
-
-
-
-
-
2.2
2.5
-
20
-
3
2.8
250
5
<tbd>
-
mV
-
pF
-
1575
mV
+100
mV
0.3VDDD(1V8) V
VDDD(1V8)
V
0.1VDDD(1V8) V
VDDD(1V8)
V
+10
A
+10
A
-
pF
-
mA
34
mA
-
mA
VDDA(3V3)
V
-
V
-
V
-
k
-
pF
-
ppm/C
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
9 of 78

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