DS3234(2006) 查看數據表（PDF） - Maxim Integrated

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DS3234
(Rev.:2006)

Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM

Maxim Integrated 

Extremely Accurate SPI Bus RTC with

Integrated Crystal and SRAM

two programmable time-of-day alarms and a program-

mable square-wave output. The INT/SQW provides either

an interrupt signal due to alarm conditions or a square-

wave output. The clock/calendar provides seconds, min-

utes, hours, day, date, month, and year information. The

date at the end of the month is automatically adjusted for

months with fewer than 31 days, including corrections for

leap year. The clock operates in either the 24-hour or 12-

hour format with AM/PM indicator. Access to the internal

registers is possible through an SPI bus interface.

A temperature-compensated voltage reference and

comparator circuit monitors the level of VCC to detect

power failures and to automatically switch to the backup

supply when necessary. When operating from the back-

up supply, access is inhibited to minimize supply cur-

rent. Oscillator, time and date, and TCXO operations can

continue while the backup supply powers the device.

The RST pin provides an external pushbutton function

and acts as an indicator of a power-fail event.

Operation

The block diagram shows the main elements of the

DS3234. The eight blocks can be grouped into four

functional groups: TCXO, power control, pushbutton

function, and RTC. Their operations are described sep-

arately in the following sections.

32kHz TCXO

The temperature sensor, oscillator, and control logic form

the TCXO. The controller reads the output of the on-chip

temperature sensor and uses a lookup table to determine

the capacitance required, adds the aging correction in

the AGE register, and then sets the capacitance selection

registers. New values, including changes to the AGE reg-

ister, are loaded only when a change in the temperature

value occurs. The temperature is read on initial applica-

tion of VCC and once every 64 seconds (default, see the

description for CRATE1 and CRATE0 in the Control/Status

Register section) afterwards.

Power Control

The power control function is provided by a tempera-

ture-compensated voltage reference and a comparator

circuit that monitors the VCC level. The device is fully

accessible and data can be written and read when VCC

is greater than VPF. However, when VCC falls below

both VPF and VBAT, the internal clock registers are

blocked from any access. If VPF is less than VBAT, the

device power is switched from VCC to VBAT when VCC

drops below VPF. If VPF is greater than VBAT, the

device power is switched from VCC to VBAT when VCC

drops below VBAT. After VCC returns above both VPF

and VBAT, read and write access is allowed after RST

goes high (Table 1).

Table 1. Power Control

SUPPLY CONDITION

READ/WRITE

ACCESS

ACTIVE

SUPPLY

VCC < VPF, VCC < VBAT

No

VCC < VPF, VCC > VBAT

Yes

VCC > VPF, VCC < VBAT

Yes

VCC > VPF, VCC > VBAT

Yes

VBAT

VCC

VCC

VCC

RST

Active

Active

Inactive

Inactive

To preserve the battery, the first time VBAT is applied to

the device, the oscillator does not start up until VCC

crosses VPF. After the first time VCC is ramped up, the

oscillator starts up and the VBAT source powers the

oscillator during power-down and keeps the oscillator

running. When the DS3234 switches to VBAT, the oscil-

lator may be disabled by setting the EOSC bit.

Pushbutton Reset Function

The DS3234 provides for a pushbutton switch to be con-

nected to the RST output pin. When the DS3234 is not in

a reset cycle, it continuously monitors the RST signal for a

low going edge. If an edge transition is detected, the

DS3234 debounces the switch by pulling the RST low.

After the internal timer has expired (PBDB), the DS3234

continues to monitor the RST line. If the line is still low, the

DS3234 continuously monitors the line looking for a rising

edge. Upon detecting release, the DS3234 forces the

RST pin low and holds it low for tRST.

The same pin, RST, is used to indicate a power-fail con-

dition. When VCC is lower than VPF, an internal power-fail

signal is generated, which forces the RST pin low. When

VCC returns to a level above VPF, the RST pin is held low

for tREC to allow the power supply to stabilize. If the

EOSC bit is set to logic 1 (to disable the oscillator in bat-

tery-backup mode), the reset signal is kept active for

tREC plus the startup time of the oscillator (typ 1 second).

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